Motor series: ultra low inertia, small capacity.
Using a serial absolute / incremental encoder.
Rated output power: 0.1kw.
Rated speed: 3000rpm.
With the brake: not with brake.
Without GB.
Shaft end: straight shaft.
The rotor of the servo motor is a permanent magnet, and the control of the servo amplifier is controlled by the U/V/W three-phase electric electromagnetic field,
The rotor rotates under the action of the magnetic field, and the encoder feedback signal of the motor is given to the driver,
According to the feedback value and the target value, the driver is compared,
Adjust the rotor rotation angle HC-SFS1024B
The accuracy of the servo motor is determined by the resolution of the encoder HC-SFS1024B. MITSUBISHI inverter FR-F720 series .
Voltage level: three phase 200V.
Frequency converter capacity: 30KW.
When the ring is opened, the frequency converter is provided with a load of the motor when the motor is operated with a load at a given frequency,
The range of the motor speed in the rated slip ratio (1%~5%) changes.
For the requirements of relatively high precision, even if the load changes are also required to operate at a given speed of the occasion,
Inverter with PG feedback function can be used (selection) HC-SFS1024B.
If the given acceleration time is too short, the output frequency of the inverter is far more than the change of the speed (electric angular frequency),
Converter will be due to flow over the current trip, the operation stopped, which is called stall. Input and output (DC/ differential).
Input points: 12 points (DC5V/DC24V/ differential universal).
Pulse input speed: the highest pulse/s 8M (2MHz).
Output points: 8 points (DC5V ~ DC24V) 6 points (differential).
Pulse output speed: the highest pulse/s 8M (2MHz).
High speed and stable input / output response
The high speed response can be achieved without the CPU module''s operation and bus performance,
Stable input and output response through hardware processing.
LD40PD01 is equipped with an external input and output interface and FPGA,
Therefore, high speed control can be realized without the influence of the scanning time of the CPU module and the bus performance (the input and output response time of the s instruction is realized).
Can achieve stablle input and output respoonse (processing time of the deviation of the ns level) HC-SFS1024B.
Through the intuitive tools for FPGA settings.
In the FPGA design process can be omitted in the past must be designed to deal with (HDL description, logic synthesis and time verification),
Reeduuce working hours HC-SFS1024B. After receiving the product can be used immediately to verify the use of special tools, can significantly shorten the design time.
HC-SFS1024B Operation manual/Instructions/Model selection sample download link: /searchDownload.html?Search=HC-SFS1024B&select=5